Previous recent disk drive designs have included, in addition to a disk data channel and a host data channel, at least one embedded digital microprocessor for controlling various functions of the disk drive such as head positioning, spindle motor speed regulation, read channel adjustments for zoned data recording and error correction tasks, and the supervision of data block transfers between disk and host in response to host commands received via the host channel. These prior designs have typically included a large data cache memory array for temporary storage of multiple data blocks in transit between the disk data storage surface and the host computing system, and smaller FIFO buffers associated with the disk data channel and the host data channel. More recently, shared use of on-board buffer memory has been extended to provide storage of instructions and data needed for microprocessor operations, with microprocessor accesses to buffer memory being multiplexed between disk channel and host channel block transfer memory accesses. These relatively large memory arrays have typically been comprised of dynamic random access memory chips (DRAM).
The DRAM memory in disk drive systems must be shared among several processes (herein referred to as "clients"). This sharing arrangement presents an interesting challenge to the designer. On the one hand, a DRAM operates most efficiently if the same client can present continuous access requests, as these requests will be sequential. A sequential request can most frequently be accomplished by accessing the DRAM in page mode. Depending upon DRAM type, page mode accesses are from three to nine times faster than non-page mode access requests. However, each client wants to obtain DRAM access as often as possible, which cuts down the length of time a particular access can be handled in page mode.
Previous disk drive designs have provided access to DRAM by the various disk drive process and resource clients via multiplexing and access arbitration. If only one client, such as the disk data channel, has a frequent, high-bandwidth "absolutely must have" need for buffer access, a simple priority scheme will suffice. The disk data channel will typically have this requirement, as the length of the disk FIFO is limited, and data will be lost if the disk channel FIFO is overrun. The other high-bandwidth channel, the host interface (SCSI or ATA), can be throttled when its FIFO is full. Thus, giving the disk channel highest priority when its FIFO is nearly full, and holding high until the disk FIFO is empty, works quite well. The host channel may have gaps. It has a lower priority, but when it obtains access to the DRAM, it holds onto its access until its FIFO is emptied or the disk channel overrides. The microprocessor, memory refresh, and other clients may be given a middle priority, for example.
One example of such a scheme is provided by commonly assigned U.S. Pat. No. 5,465,343 to Henson et al., entitled: "Shared Memory Array for Data Block and Control Program Storage in Disk Drive", the disclosure thereof being incorporated herein by reference. In this prior approach buffer memory access arbitration followed a hierarchical approach with each internal client seeking buffer access having a defined priority. For example, the disk data channel was given the highest priority, since data transfers to and from the disk must be made in synchronism with storage disk rotation in order not to incur delays caused by multiple disk rotation latencies during a data transfer. A next level priority was accorded to a dynamic memory array cell refresh function. A third level priority was accorded either to a host interface client or to a control microprocessor client, depending upon buffer manager programming and required memory bandwidths of the respective client processes. In implementations of the Henson et al. approach within disk drives, round-robin schemes have been used, so that if all channels are requesting DRAM access, each channel is serviced in a fixed order for a set maximum length of time. If any channel is not requesting access, the next channel in the priority sequence takes over, and so on. In any of these schemes at no time does the DRAM sit idle if there is an unserviced request for access from any channel. The problem with this prior scheme is that all numbers have to be set for the worst case, and maximum advantage is not taken on rounds where the worst-case does not occur.
Another drawback of the Henson et al. arbitration approach arose from the fact that the microprocessor's instruction and data access patterns to the shared memory array were unlike disk channel and host channel data block transfer access patterns. The disk channel and host channel clients have large sequential block accesses to the buffer memory via multi-word FIFOs and thus are suitable candidates for fast, page mode transfer requests. In contrast, the microprocessor typically fetches a single instruction from a segment (full buffer address) of the buffer and decodes the instruction in order to determine what further accesses it needs to the buffer memory. The instruction decode process may cause a delay in a subsequent buffer memory access request by the microprocessor. In the Henson et al. prior approach, the delay during instruction decode resulted in the microprocessor losing control of the buffer memory to another client, such as disk channel or host channel which did not critically require buffer memory access, but which had data available for transfer from FIFO to the buffer, or which had available FIFO space to receive data from the buffer. The loss of buffer memory access by the microprocessor in favor of data block transfers to disk channel FIFO or host channel FIFO not operating at full utilization produced a loss of efficiency in the buffer management process, and thus lowered the buffer memory resource available to the microcontroller. In many disk drive data transfer systems, the disk channel and the host channel will have their data block transfer requirements satisfied, but the embedded microprocessor controller will not.
It is known within general digital data computer designs to provide blended priority and round-robin bus arbitration schemes. One example is provided by U.S. Pat. No. 5,581,782 to Sarangdhar et al, entitled: "Computer System with Distributed Bus Arbitration Scheme for Symmetric and Priority Agents". This prior bus arbitration protocol supported both symmetric (round-robin) clients and priority clients. The symmetric clients were prioritized in a circular order of priority to equalize access to memory via the bus on a rotating basis. A priority client could claim ownership of the bus and override new access requests by a symmetric client, unless the request was part of an ongoing bus-locked operation. Another round-robin arbitration protocol was provided in U.S. Pat. No. 5,533,205 to Blackledge, Jr., et al., entitled: Method and System for Efficient Bus Allocation in a Multimedia Computer System". In this prior approach individual input/output devices were given bus access arbitration priority in a round-robin sequence so that each device obtained bus access at a minimum required data transfer rate needed to maintain proper multimedia presentation quality. While these prior approaches may have worked well within multiprocessor and multimedia computing environments respectively, they were not adapted to the unique problems and challenges of buffer management which have been discovered to be present within a hard disk drive.
The present invention provides a solution to the hitherto unsolved problems associated with arbitrating accesses to a shared memory array within a disk drive.